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| HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com features switch mode controller for single-switch converters gate drivers optimized for driving logic level fets ? 0.25a sourcing ? 0.5a sinking typical 2% absolute and string-to-string current accuracy (with 1% sense resistors) high pwm dimming ratio up to 5000:1 10-40v input range constant frequency operation up to 1.0mhz on-chip clock or external clock option programmable slope compensation linear and pwm dimming output short circuit protection output over voltage protection hiccup mode protection applications rgb backlight applications boost, buck & sepic topologies multiple string white led driver applications ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the HV9985 is a three-channel peak current mode pwm controller for driving single switch converters in a constant output current mode. it can be used for driving either rgb leds or multiple channels of white leds. the HV9985 features a 40v linear regulator, which provides a 5.0v supply to power the ic. the switching frequencies of the three converters in the ic are controlled either with an external clock signal (the channels operate at a switching frequency of 1/12th of the external clock frequency) or using the internal oscillator. the three channels are positioned 120 out-of-phase to reduce the input current ripple. each converter is driven by a peak current mode controller with output current feedback. the three output currents can be individually dimmed using either linear or pwm dimming. the ic also includes three disconnect fet drivers which enable high pwm dimming ratios and also helps to disconnect the input in case of an output short circuit condition. the HV9985 includes hiccup mode protection for both open led and short circuit condition to prevent the ic from shutting down in the case of intermittent faults. three-channel, closed-loop, switch mode led driver ic typical application circuit l1 q1 a d1 a c o1 c in q1 b r s r ref 1 c c1 c ref1 r t c vdd c sc1 c in 1 r sc1 d1b (optional) re f c skip c vdd1 r cs 1 r ovp1b r ovp1a gt1 cs 1 vd d vi n gn d ovp1 fdbk 1 flt 1 ref1 rt HV9985 (one channel shown) vdd1 gnd1 skip en comp1 cl k pwmd 1
2 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device 40-lead qfn 6.00x6.00mm body 1.00mm height (max) 0.50mm pitch 44-lead qsop 17.83x7.50mm body 2.64mm height (max) 0.80mm pitch HV9985 HV9985k6-g HV9985qp-g absolute maximum ratings parameter value vin to gnd -0.3v to +45v vdd to gnd, vdd 1-3 to gnd -0.3v to +6.0v all other pins to gnd -0.3v to (v dd + 0.3v) junction temperature -40c to +125c storage ambient temperature range -65c to +150c continuous power dissipation (t a = +25c) 4000mw stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speci?cations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin con?gurations -g indicates package is rohs compliant (green) vdd1 flt1 cs1 comp1 fbdk1 ref1 ovp 1 vin vdd enn gate1 gnd1 fdbk cs2 flt2 gate2 gnd2 vdd 2 gnd3 gate3 gnd comp2 ref 2 ovp2 ski p nc pwmd1 nc pwmd2 pwmd3 vdd3 flt3 cs3 fbdk 3 ref3 ovp 3 clk rt nc comp3 gnd 1 40 HV9985 llllll yyww aaacc c l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packaging product marking 40-lead qfn (k6) (top view) 40-lead qfn (k6) package may or may not include the following marks: si or thermal resistance package ja 40-lead qfn 18 o c/w 44-lead qsop 50 o c/w ja for qfn package is based on a 4 layer pcb as per jesd51-9 ja for qsop package is based on a 4 layer pcb as per jesd51-7 44-lead qsop (qp) (top view) ref1 ovp1 vin vdd en nc gnd nc comp2 ref2 ovp2 skip nc pwmd1 pwmd2 pwmd3 nc nc rt clk ovp3 ref3 fdbk1 comp1 cs 1 ft 1 vdd1 nc ga te 1 gnd1 fdbk2 cs 2 ft 2 ga te 2 gnd2 vdd2 gnd3 ga te 3 nc vdd3 ft 3 cs 3 comp3 fdbk3 1 44 44-lead qsop (qp) package may or may not include the following marks: si or yy = year sealed ww = week sealed l = lot number c = country of origin a = assembler id* = green packagin g *may be part of top markin g top marking bottom marking y y w w a a a h v 9 9 8 5 q p l l l l l l l l l l ccccccccccc 3 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym parameter min typ max units conditions input v indc input dc supply voltage * 10 - 40 v dc input voltage i insd shut-down mode supply current * - - 200 a en 0.8v i in supply current - - - 1.0 ma en 2.0v; pwmd1 = pwmd2 = pwmd3 = gnd internal regulator v dd internally regulated voltage * 4.75 5.00 5.25 v v in = 10 - 40v; en = high; pwmd1-3 = v dd ; gate1-3 = 1.0nf; clk = 6mhz uvlo rise v dd under voltage lockout threshold - 4.25 - 4.75 v v dd rising uvlo hyst v dd under voltage hysteresis - - 250 - mv v dd falling enable input v en(lo) en input low voltage * - - 0.8 v --- v en(hi) en input high voltage * 2.0 - - v --- r en en pull down resistor - 50 100 150 k? v en = 5.0v pwm dimming (pwmd1, pwmd2 and pwmd3) v pwmd(lo) pwmd input low voltage * - - 0.8 v --- v pwmd(hi) pwmd input high voltage * 2.0 - - v --- r pwmd pwmd pull down resistor - 50 100 150 k? v pwmd = 5.0v gate (gate1, gate2 and gate3) i source gate short circuit current, sourcing # 0.25 - - a v gate = 0v i sink gate sinking current # 0.5 - - a v gate = v dd t rise gate output rise time * - - 85 ns c gate = 2.0nf t fall gate output fall time * - - 45 ns c gate = 2.0nf d max maximum duty cycle # - 91.7 - % --- over voltage protection (ovp1, ovp2 and ovp3) v ovp,rising over voltage rising trip point * 1.13 1.25 1.37 v ovp rising v ovp,hyst over voltage hysteresis - - 125 - mv ovp falling current sense (cs1, cs2 and cs3) t blank leading edge blanking * 100 - 250 ns --- t delay delay to output of gate - - - 200 ns 100mv overdrive to the current sense comparator r dis discharge resistance for slope compensation * - - 300 ? gate = low # denotes speci?cations guaranteed by design. * the speci?cations which apply over the full operating temperature range at 0 o c < t a < +85 o c are guaranteed by design and characterization. electrical characteristics (the * denotes the speci?cations which apply over the full operating ambient temperature range 0 o c 6 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com functional description power topology the HV9985 is a three-channel, switch-mode converter led driver designed to control a boost, a buck or a sepic con - verter in a constant frequency, peak current controlled mode. the ic includes an internal linear regulator, which operates from input voltages 10 to 40v. the ic can also be powered directly using the vdd pins and bypassing the internal linear regulator. the ic includes features typically required in led drivers like open led protection, output short circuit protec - tion, linear and pwm dimming, and accurate control of the led current. the ic is ideally suited for backlight applica - tion using either rgb or multi-channel white led con?gura - tions. power supply to the ic (vin, vdd, vdd1-3) the HV9985 can be powered directly from its vin pin that takes a voltage up to 40v. when a voltage is applied at the vin pin, the HV9985 tries to maintain a constant 5.0v (typ.) at the vdd pin. the regulator also has a built in under-volt - age lockout which shuts the ic off if the voltage at the vdd pin falls below the uvlo threshold. by connecting this vdd pin to the individual vdd pins of the three channels, the internal regulator can be used to power all three channels in the ic. in case the internal regulator is not utilized, an external pow - er supply (5.0v +/- 10%) can be used to power the ic. in this case, the power supply is directly connected to the vdd pins and the vin pin. all four vdd pins must by bypassed by a low esr capaci - tor (0.1f) to provide a low impedance path for the high frequency current of the output gate driver. these capaci - tors must be referenced to the individual grounds for proper noise rejection (see layout guidelines section for more in - formation). also, in all cases, the four vdd pins must be con - nected together externally. the input current drawn from the external power supply (or vin pin) is a sum of the 1.0ma (max) current drawn by the all the internal circuitry (for all three channels) and the cur - rent drawn by the gate drivers (which in turn depends on the switching frequency and the gate charge of the external fet). i in = 1ma + (q g1 +q g2 + q g3 ) ? f s in the above equation, f s is the switching frequency of the converters and q g1-3 are the gate charges of the external fets (which can be obtained from the fet datasheets). the en pin is a ttl compatible input used to disable the ic. pulling the en pin to gnd will shut down the ic and reduce the quiescent current drawn by the ic to be less than 300a. if the enable function is not required, the en pin can be con - nected to vdd. clock input (clk) the switching frequency of the converters can be set in one of two ways. one way to set the switching frequency is to use the on-chip oscillator using a resistor at the rt pin. in this case, the clk pin should be connected to gnd. if the on-chip clock is used, two or more HV9985s cannot be syn - chronized to each other. the other way to is set the switching frequency by using a ttl compatible square wave input at the clk pin. the switching frequencies of the three converters will be 1/12th the frequency of the external clock. by using the same clock for multiple ics, all the ics can be synchronized together. in this case, the rt pin can be either left open or connected to gnd. current sense (cs1-3) the current sense input is used to sense the source current of the switching fet. each cs input of the HV9985 includes a built-in 100ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the fet turns on. the ic includes an internal resistor divider network, which steps down the voltage at the comp pins by a factor of 9. this voltage is used as the reference for the current sense comparators. since the maximum voltage of the comp pin is approximately (v dd C1.0v), this voltage determines the maximum reference current for the current sense compara - tor and thus the maximum inductor current. the current sense resistor r cs should be chosen so that the input inductor current is limited to below the saturation cur - rent level of the input inductor. for discontinuous conduction mode of operation, no slope compensation is necessary. in this case, the current sense resistor is chosen as: r cs = v dd C 1v 9 ? i in,pk where i in,pk is the maximum desired peak input current. for continuous conduction mode converters operating in the constant frequency mode, slope compensation becomes necessary to ensure stability of the peak current mode con - troller, if the operating duty cycle is greater than 50%. this factor must also be accounted for when determining r cs (see slope compensation section). 7 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com slope compensation fig. 1. slope compensation choosing a slope compensation which is one half of the down slope of the inductor current ensures that the convert - er will be stable for all duty cycles. slope compensation in the HV9985 can be programmed by two external components (see fig. 1). a resistor for vdd sets a current (which is almost constant since the vdd volt - age is much larger than the voltage at the cs pin). this current ?ows into the capacitor and produces a ramp volt - age across the capacitor. the voltage at the cs pin is then the sum of the voltage across the capacitor and the voltage across the current sense resistor, with the voltage across the capacitor providing the required slope compensation. when the gate turns off, an internal pull down fet discharges the capacitor. the 30 resistance of the internal fet (rdis) will prevent the voltage at the cs pin from going all the way to zero. the minimum value of the voltage will instead be: v cs,min = v dd ? r dis r sc the slope compensation capacitor is chosen so that it can be completely discharged by the internal fet at the cs pin during the time the fet is off. assuming the worst case switch duty cycle of 92%, c sc = 0.08 3 ? r dis ? f s assuming a down slope of ds (a/ s) for the inductor current, the current sense resistor and the slope compensation resis - tor can be computed as : note: sometimes, excessive stray inductance in the current sense path may cause the slope compensation circuit to mistrigger. the following section describes the cause of the problem and the solution. fig. 2 shows the detailed slope compensation circuit with a parasitic inductance l p between the ground of the boost converter and the ground of the respective channel in the HV9985. also shown is the drain capacitance of the boost fet q1 (which is the total capacitance at the drain node). fig. 2: slope compensation circuit operation when the fet is off, the internal discharge fet q2 is turned on and capacitor c sc is discharged. also, c drain is charged to the output voltage v o . when the fet is turned on, the drain node of the fet is pulled to ground (q2 is turned off just prior to q1 being turned on). this causes the drain ca - pacitance to discharge through the fet causing a current spike as shown in fig. 3. this current spike causes a volt - age to develop across the parasitic inductance. as long as the current is increasing through the inductance, the volt - age developed across the inductor is successfully blocked by the body diode of q2. however, during the falling edge of the current spike, the voltage across the inductor causes the body diode to become forward biased. this conduction path through the body diode of q2 causes pre-charge of c sc . the pre-charge voltage can be fairly high since the rate of fall of the current is very large. fig. 3: waveforms during turn-on cs vd d r sc c sc r cs + - gate r cs = v dd - 1 9 ? 1 ds ? 10 6 ? 0.92 2 ? f s + i in,p k r sc = 2 ? v dd ds ? 10 6 ? c sc ? r cs cs vdd r sc c sc r cs + - ga te gate gn d l p i lp - v lp + + v drain - c drain q1 q2 v drai n i lp v lp 8 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com for example, a typical current spike usually lasts about 100ns. assuming a 3.0a peak current (this value is usually the saturation current of the fet which can be much higher) and equal distribution between the rise and fall times, a 10nh parasitic inductance causes a pre-charge voltage of: v pre-charge = 10nh ? 3a = 600mv 50ns as can be seen, a very optimistic estimate of the pre-charge voltage is already larger than the steady state peak current sense voltage and will cause the converter to false trip. to prevent this behavior, a resistor (typically 500 C 800?) can be added in series with the capacitor as shown in fig. 4. this resistor limits the charging current into the capacitor. however, the resistor will also slow down the discharge of the capacitor during the fet off time, so a smaller c sc will be necessary. the values can be computed by substituting r ext + r dis in place of r dis in the above equations. fig. 4: modi?ed slope compensation circuit control of the led current the led currents in the HV9985 are controlled using three independent current feedbacks. the reference voltage in - puts, which set the three led currents, should be provided at each ref pin (ref1-3). these reference voltages are compared to the voltage from the led current sense resis - tors at the corresponding fdbk pins (fdbk1-3). HV9985 includes three 1.0mhz transconductance ampli?ers with tri- state output, which are used to close the feedback loops and provide accurate current control. the compensation net - works are connected at the comp pins (comp1-3). the output of each op-amp is buffered and connected to the current sense comparators using an 8:1 divider. the outputs of the op-amps are controlled by the signal ap - plied to the pwmd pins (pwmd1-3). when pwmd is high, the output of the opamp is connected to the comp pin. when pwmd is low, the output is left open. this enables the inte - grating capacitor to hold the charge when the pwmd signal is low, and the gate driver output (gate1-3) is off. when the ic is enabled, the voltage on the integrating capacitor will force the converter into steady state almost instantly. linear dimming linear dimming can be accomplished in the HV9985 by varying the voltages at the ref pins. since the HV9985 is a peak current mode controller, it has a minimum on-time for the gate outputs. this minimum on-time will prevent the converters from completely turning off even when the ref pins are pulled to gnd. thus, linear dimming cannot accom - plish true zero led current. to get zero led current pwm dimming has to be used. different signals can be connected to the three ref pins if desired, and these inputs need not be connected together. due to the offset voltage of the short circuit comparator as well as the non-linearity of the x2 gain stage, pulling the ref pin very close to gnd would cause the internal short circuit comparator to trigger and shut down the ic. to over - come this, the output of the gain stage is limited to 125mv (minimum), allowing the ref pin to be pulled all the way to 0v without triggering the short circuit comparator. pwm dimming pwm dimming in the HV9985 can be accomplished by us - ing ttl compatible square wave sources at the pwmd pins (pwmd1-3). all three channels can be individually pwm dimmed as desired. when the pwm signal is high, the gate and flt pins are enabled and the output of the transconductance opamp is connected to the external compensation network. thus, the internal ampli?er controls the output current. when the pwmd signal goes low, the output of the transconductance ampli?er is disconnected from the compensation network. thus, the integrating capacitor maintains the voltage across it. the gate is disabled, so the converter stops switching, and the flt pin goes low, turning off the disconnect switch. the output capacitor of the converter determines its pwm dimming response, since it has to get charged and dis - charged whenever the pwmd signal goes high or low. in the case of a buck converter, since the inductor current is con - tinuous, a very small capacitor is used across the leds. this minimizes the effect of the capacitor on the pwm dimming response of the converter. however, in the case of a boost converter, the output current is discontinuous and a large output capacitor is required to reduce the ripple in the led current. thus, this capacitor will have a signi?cant impact on the pwm dimming response. by turning the disconnect switch off when pwmd goes low, the output capacitor is pre - vented from being discharged, and thus the pwm dimming response of the boost converter improves dramatically. vdd r sc c sc r cs + - gate gate gnd l p i lp - v lp + + v drain - c drain q1 q2 cs r ex t 9 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com note that disconnecting the led load during pwm dimming causes the energy stored in the inductor to be dumped into the output capacitor. the ?lter capacitor should be chosen large enough so that it can absorb the inductor energy with - out signi?cant change of the voltage across it. fault conditions the HV9985 is a robust controller which can protect the leds and the led driver in case of fault conditions. the out - puts of the HV9985 led driver are protected from both an open and a short led condition. in both cases, the HV9985 shuts down and attempts a restart. the hiccup time can be programmed by a single external capacitor at the skip pin. during start-up or when a fault condition is detected, both gate and flt outputs are disabled, the comp and skip pins are pulled to gnd. once the voltage at the skip pin falls below 0.1v, and the fault condition(s) have disappeared, the capacitor at the skip pin is released, and it begins charging slowly from a 5.0a current source. once the capacitor is charged to 2.0v, the comp pins are released, and the gate driver outputs (gate and flt) are allowed to turn on. if the hiccup time is long enough, it will ensure that the compen - sation networks are all completely discharged and that the converters start at minimum duty cycle. the hiccup timing capacitor can be programmed as: c ramp = 5a ? t hiccup 2v output short circuit protection when a short circuit condition is detected (output current be - comes higher than twice the steady state current), the gate and flt outputs are pulled low. as soon as the disconnect fet is turned off, the output current goes to zero and the short circuit condition disappears. at this time, the hiccup timer is started. once the timing is complete, the converter attempts to restart. if the fault condition still persists, the converter shuts down and goes through the cycle again. if the fault condition is cleared (a momentary output short) the converter will start regulating the output current normally. this allows the led driver to recover from accidental shorts without the need to reset the ic. during short circuit conditions, there are two factors that de - termine the hiccup time. the ?rst is the time required to discharge the compensation capacitors. assuming a pole-zero r-c network at the comp pin (series combination of r z and c z in parallel with c c ), t comp,n = 3 ? r zn ? c zn where n refers to the channel number. in case the compensation networks are only of type 1 (sin - gle capacitor), then: t comp,n = 3 ? 300 ? c zn thus, the maximum comp discharge time required can be computed as: t comp,max = max (t comp1 , t comp2 , t comp3 ) the second factor is the time required for the inductors to discharge completely after the short circuit condition has been cleared. this time can be computed as: t ind,n = l n ? c on 4 where l and c o are the input inductor and output capacitor of each power stage. thus, the maximum time required for the inductors to dis - charge can be computed as: t ind,max = max (t ind1 , t ind2 , t ind3 ) the hiccup time is then chosen as: t hiccup > max (t comp,max , t ind,max ) false triggering of the short circuit comparator during pwm dimming during pwm dimming, the parasitic capacitance of the led string causes a spike in the output current when the discon - nect fet is turned on. if this spike is detected by the short circuit comparator, it will cause the ic to falsely detect an over current condition and shut down. in the HV9985, to prevent these false triggerings, a built-in 500ns blanking network for the short circuit comparator is in - cluded. this blanking network is activated when the pwmd input goes high. thus, the short circuit comparator will not see the spike in the led current during the turn-on transi - tion of the pwm dimming. once the blanking time is over, the short circuit comparator will start monitoring the output current. thus, the total delay time for detecting a short circuit will depend on the condition of the pwmd input. if the output short circuit exists before the pwm dimming signal goes high, the total detection time will be: t detect1 = t blank + t delay 900ns(max) 10 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com if the short circuit occurs when the pwm dimming signal is already high, the time to detect will be: t detect1 = t delay 200ns(max) over voltage protection the HV9985 provides hysteretic over voltage protection, allowing the ic to recover in case the led load is discon - nected momentarily. when the load is disconnected in a boost converter, the output voltage rises as the output capacitor starts charging. when the output voltage reaches the ovp rising threshold, the HV9985 detects an over voltage condition and turns off the converter. the converter is turned back on only when the output voltage falls below the falling ovp threshold (which is 10% lower than the rising threshold). this time is mostly dictated by the r-c time constant of the output capacitor c o and the resistor network used to sense over voltage (r ovp1 + r ovp2 ). in case of a persistent open circuit condition, this cycle maintains the output voltage within a 10% band. in most designs, the falling ovp threshold will be more than the led string voltage. thus, when the led load is recon - nected to the output of the converter, the voltage differential between the actual output voltage and the led string volt - age will cause a spike in the output current. this causes a short circuit to be detected, and the short circuit protection in the HV9985 will be triggered. this behavior continues until the output voltage becomes lower than the led string volt - age. when this occurs, no fault will be detected, and normal operation of the circuit will commence. note: the overvoltage thresholds for the three channels in the HV9985 are derived by using resistor dividers from the re - spective vdds. the resistor dividers are adjusted to give a 1.25v ovp rising trip point and a 1.125v ovp falling trip point at v dd = 5.0v. the ovp trip points mentioned in the electrical characteristics table of the datasheet as - sume a v dd voltage generated by the linear regulator of the HV9985. using an external voltage source at vdd will change the ovp trip points proportionally. layout considerations for multi-channel peak current mode controller ic to work properly with minimum interference between the channels, it is important to have a good pcb layout which minimizes noise. following the layout rules stated below will help to ensure proper performance of all three channels. 1. gnd connection the ic has four separate ground connections - one for each of the three channels and one analog ground for the common circuitry. it is recommended that four sepa - rate ground planes be used in the pcb, and all the gnd planes be connected together at the return terminal of the input power lines. 2. vdd connection each vdd pin should be bypassed with a low esr ca - pacitor to its own ground (i.e. vdd1 is bypassed to gnd1 and so on). the common vdd pin can be by - passed to the common gnd. 3. ref connection in case all the references are going to be driven from a single voltage source, it is recommended to have a small r-c low pass ?lter (1.0k, 1.0nf) at each ref pin with the ?lter being referenced to the appropriate channels ground (as in the case of the vdd pins). if the ref pins are driven with three individual voltage sources, then just a small capacitor (1.0nf) at each pin would suf?ce. 4. gate and cs connection the connection from gate output to the gate of the ex - ternal fet as well as the connection from the cs pin to the external sense resistor made as short as possible to avoid false trigerrings. 5. ovp protection typically, the ovp resistor dividers would be located away from the ic. to prevent false trigerrings of the ic due to noise at the ovp pin, a small bypass capacitor (1.0nf) right at the ovp pin is recommended. 11 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com layout guidelines vdd1 vdd 2 vdd 3 vdd gnd gnd1 gnd2 gnd3 ref1 ref3 ref2 hv998 5 input return terminal referenc e sta r connection of gn d vdd connection re f connection gnd ta b connection 12 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin description (k6) pin # name description 1 vdd1 these pins are the power supply pins of the three channels. they can either be connected to the vdd pin or supplied with an external power supply. they must be bypassed with a low esr capacitor to their respective gnds (at least 0.1f). all vdd pins (vdd, vdd1-3) must be connected together externally. an external 5.0v supply can be connected to these pins to power the ic if the internal regulator is not used. 33 vdd2 30 vdd3 2 flt1 these pins are used to drive external logic-level disconnect switches. the disconnect switches are used to protect the leds in case of fault conditions and also serve to provide excellent pwm dimming re - sponse by disconnecting and reconnecting the leds from the output capacitor during pwm dimming. 36 flt2 29 flt3 3 cs1 these pins are used to sense the source current of the external power fets. they include a built-in 100ns (min) blanking timer. connecting an rc-network at these pins programs the slope compensation. refer to the slope compensation section for additional information. 37 cs2 28 cs3 4 comp1 stable closed loop control can be accomplished by connecting a compensation network between each comp pin and its respective gnd. 12 comp2 27 comp3 5 fdbk1 these pins are the output current feedback inputs for each channel. they receive voltage signal from external sense resistors. 38 fdbk2 26 fdbk3 6 ref1 the voltage at this pin sets the output current level for channel 1. recommended voltage range for this pin is 0 C 1.25v. 13 ref2 25 ref3 7 ovp1 these pins provide the over voltage protection for the three channels. when the voltage at any of these pins exceeds 1.25v, the HV9985 is turned off. the fault timer starts when the voltage drops below 1.125v. upon completion of the fault timer the ic attempts to restart. 14 ovp2 24 ovp3 8 vin input of the internal 40v linear regulator. 9 vdd this pin is the output of the linear regulator. it maintains a regulated 5.0v as long as the voltage of the vin pin is between 10v and 40v. it must be bypassed with a low esr capacitor to gnd (at least 0.1f). this pin can be used as a power supply for the three channels. 10 en when the pin is pulled below 0.8v, then ic goes into a standby mode and draws minimal current. 11 gnd ground connection for the common circuitry in the HV9985. 15 skip this pin programs the hiccup timer for fault conditions. a capacitor to gnd programs the hiccup time. 16 nc no connect. 17 pwmd1 pwm dimming of the three channels is accomplished by using the pwmd pins. the three pins directly control the pwm dimming of the three channels and a square wave input should be applied at these pins. 18 pwmd2 19 pwmd3 20 nc no connect. 21 13 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # name description 22 rt a resistor at this pin programs the on-board oscillator. if an external clock is being used, this pin should be connected to vdd. 23 clk this pin is the clock input for the HV9985. the input to the clk pin should be a ttl compatible square wave signal. the three channels will switch at 1/12th the switching frequency of the signal applied at the clk pin. this pin is used if more than one HV9985s are being used in a system. if the on-chip oscillator is being used, this pin should be connected to gnd. 40 gate1 these pins are the gate drivers which drive the external logic-level, n-channel boost converter mos - fets. 35 gate2 31 gate3 39 gnd1 ground return for each of the channels. it is recommended that all the gnds of the ic be connected together in a star connection at the input gnd terminal to ensure best performance. 34 gnd2 32 gnd3 pin description (k6) (cont.) pin # name description 40 vdd1 these pins are the power supply pins of the three channels. they can either be connected to the vdd pin or supplied with an external power supply. they must be bypassed with a low esr capacitor to their respective gnds (at least 0.1f). all vdd pins (vdd, vdd1-3) must be connected together externally. an external 5.0v supply can be connected to these pins to power the ic if the internal regulator is not used. 31 vdd2 27 vdd3 41 ft1 these pins are used to drive external logic-level disconnect switches. the disconnect switches are used to protect the leds in case of fault conditions and also serve to provide excellent pwm dimming re - sponse by disconnecting and reconnecting the leds from the output capacitor during pwm dimming. 34 ft2 26 ft3 42 cs1 these pins are used to sense the source current of the external power fets. they include a built-in 100ns (min) blanking timer. connecting an rc-network at these pins programs the slope compensation. refer to the slope compensation section for additional information. 35 cs2 26 cs3 43 comp1 stable closed loop control can be accomplished by connecting a compensation network between each comp pin and its respective gnd. 9 comp2 24 comp3 44 fdbk1 these pins are the output current feedback inputs for each channel. they receive voltage signal from external sense resistors. 36 fdbk2 23 fdbk3 1 ref1 the voltage at this pin sets the output current level for channel 1. recommended voltage range for this pin is 0 C 1.25v. 10 ref2 22 ref3 2 ovp1 these pins provide the over voltage protection for the three channels. when the voltage at any of these pins exceeds 1.25v, the HV9985 is turned off. the fault timer starts when the voltage drops below 1.125v. upon completion of the fault timer the ic attempts to restart. 11 ovp2 21 ovp3 pin description (qp) 14 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin # name description 3 vin input of the internal 40v linear regulator. 4 vdd this pin is the output of the linear regulator. it maintains a regulated 5.0v as long as the voltage of the vin pin is between 10v and 40v. it must be bypassed with a low esr capacitor to gnd (at least 0.1f). this pin can be used as a power supply for the three channels. 5 en when the pin is pulled below 0.8v, then ic goes into a standby mode and draws minimal current. 7 gnd ground connection for the common circuitry in the HV9985. 12 skip this pin programs the hiccup timer for fault conditions. a capacitor to gnd programs the hiccup time. 6 nc no connect. 8 13 17 18 28 39 14 pwmd1 pwm dimming of the three channels is accomplished by using the pwmd pins. the three pins directly control the pwm dimming of the three channels and a square wave input should be applied at these pins. 15 pwmd2 16 pwmd3 19 rt a resistor at this pin programs the on-board oscillator. if an external clock is being used, this pin should be connected to vdd. 20 clk this pin is the clock input for the HV9985. the input to the clk pin should be a ttl compatible square wave signal. the three channels will switch at 1/12th the switching frequency of the signal applied at the clk pin. this pin is used if more than one HV9985s are being used in a system. if the on-chip oscillator is being used, this pin should be connected to gnd. 38 gate1 these pins are the gate drivers which drive the external logic-level, n-channel boost converter mos - fets. 33 gate2 29 gate3 37 gnd1 ground return for each of the channels. it is recommended that all the gnds of the ic be connected together in a star connection at the input gnd terminal to ensure best performance. 32 gnd2 30 gnd3 pin description (qp) (cont.) 15 HV9985 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 40-lead qfn package outline (k6) 6.00x6.00mm body, 1.00mm height (max), 0.50mm pitch notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1. 2. 3. seating plane to p v iew side v iew bottom v iew a a1 d e b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 40 1 40 e d2 symbol a a1 a3 b d d2 e e2 e l l1 o dimension (mm) min 0.80 0.00 0.20 ref 0.18 5.85* 1.05 5.85* 1.05 0.50 bsc 0.30 ? 0.00 0 nom 0.90 0.02 0.25 6.00 - 6.00 - 0.40 ? - - max 1.00 0.05 0.30 6.15* 4.45 6.15* 4.45 0.50 ? 0.15 14 jedec registration mo-220, variation vjjd-6, issue k, june 2006. * this dimension is not speci?ed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-40qfnk66x6p050, version c041009. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2009 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 16 HV9985 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-HV9985 a062409 44-lead qsop package outline (qp) 17.83x7.50mm body, 2.64mm height (max), 0.80mm pitch symbol a a1 a2 b d e e1 e l l1 l2 1 dimensions (mm) min 2.44 0.10 2.34 0.28 17.73 10.11 7.40 0.80 ref 0.40 1.405 ref 0.355 bsc 0 o 7 o typ nom - - - - - - - - - max 2.64 0.30 2.54 0.51 17.93 10.51 7.60 1.27 8 o drawings are not to scale. supertex doc. #: dspd-44qsopqp, version a062309. d seating plane gauge plane l l1 l2 to p v iew side v iew vi ew a-a vi ew b vi ew b 1 e1 e a a2 a1 a a seating plane b 44 1 e note 1 (index area d/2 x e1/2) note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1. |
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